VHDL DIGITAL DESIGN
VHDL is a Hardware Description Language (HDL) used to describe and test digital circuits and systems, and is the practical method used in the industry to design digital systems.
This workshop views the digital design flow process, demonstrates different VHDL design styles and illustrates coding of different well-known digital blocks. We also explore how to test digital circuits and VHDL entities.
The practical aspect is well-covered with extensive exercises on Mentor Modelsim.
Prerequisites: good knowledge with digital circuits (i.e. logic design course)
- Digital Designing Introduction.
- Introduction to the VHDL language and ModelSim tool.
- VHDL design styles
- Behavioral Coding
- Finite State Machines (FSM) And Algorithmic State Machines (ASM)
- Test Benches
- Pipelining Technique.